In the fabrication of semiconductor devices, aspects of required features can vary from the design characteristics due to a variety of causes. For example, features are often altered due to optical and etch difficulties. Among such variations, the length, width and position of a feature can be altered, corners may be rounded, and isolated lines can differ in their reproduction from identical lines surrounded by other features. Of particular concern is the foreshortening or decrease in actual length versus design length of a line or space, which can result in a plurality of problems as for example, opens between two metal levels, incorrect emitter open areas and shorting between features due to a failed intersection of deep trenches. Consequently, while the determination of the width or location of a feature is of importance, the determination of its length is often also vital for process control in the fabrication of semiconductors.
As expected, the above noted irregularities significantly complicate process control in the manufacture of integrated circuits. Presently, the increasingly smaller chip configurations expand the difficulties in providing precise features, and generally render present measurement techniques unsatisfactory. For instance, while the dimensions of a feature can be determined utilizing standard measurement techniques, such as by use of a Scanning Electron Microscope (SEM), the reduced size of the replicated features require ever more stringent calibration of such devices, and the latter measurement techniques still remain limited in precision, and in any event, are time consuming.
Electrical test structures, such as the basic bridge cross test resistor, are widely utilized for line width testing. Further, a standard electrical test structure can be used to measure width of a feature. Other electrical measurement techniques are available, for example, U.S. Pat. No. 3,974,443 teaches forming a pair of lines of different width interconnected for electrical comparison to determine the width of one of the lines, U.S. Pat. No. 4,516,071 describes the measurements of lines using a test pattern combining a Van der Pauw type cross resistor, a bridge resistor, and a longitudinally split-bridge resistor, and IBM Technical Disclosure, Vol. 32, No. 12, May 1990, teaches fabrication of a test structure designed for measuring both spaces and lines.
However, these test structures often require interconnection with the feature, and thus, in themselves can cause variations in the printed feature. That is, in some configurations, the printed length of a feature varies in accordance with the location of other features in its vicinity such that it must be printed in isolation to avoid foreshortening. Consequently, the amount of foreshortening exhibited by the feature may be dependent on whether the feature is printed in isolation or in the vicinity of other features required for the electrical measurement.
Additionally, U.S. Pat. No. 4,871,962 teaches the measurement of the width of square openings or the diameter of circular openings formed within a conductive line by measuring and comparing the resistance of the line with the resistance of an identical line without the openings. This, in turn, permits calculation of the width or diameter of the openings. The arrangement requires printing of the feature within the test line, and does not appear to be well suited to measuring of an elongated feature.
Accordingly, there exist a need for an improved testing technique which obviates the problems of the prior art and furnishes an electrical test structure and method for determining dimensional characteristics of a printed feature while minimizing distortion from the design specification for that feature.